1. Field of the Invention
The present invention relates to a semiconductor memory device. The invention relates to, for example, a semiconductor memory device which includes a memory cell having a charge accumulation layer and a control gate.
2. Description of the Related Art
Up to this time, an electrically erasable and programmable ROM (EEPROM) has been known as a nonvolatile semiconductor memory capable of electrically rewriting data therein. A NAND-type flash memory has been known as an EEPROM in which a large capacity and high integration can be attained.
Recently, the NAND-type flash memory has been required to accelerate its operation. For instance, Jpn. Pat. Appln. KOKAI Publication No. 2005-142431 has disclosed a configuration which lowers the resistance of a source line in order to accelerate an operation of reading data. According to this configuration, the NAND-type flash memory may enlarge the wiring width of a region to which currents are collected in the source line, and it results in lowering the resistance of the source line.
However, it is hard for the NAND-type flash memory of such a configuration to improve, for instance, the drive ability of a source line driver. The NAND-type flash memory of such a configuration may not fully reduce the resistance of the source line sometimes.